The hardware savings also stem from AWS’s careful implementation of an operation known as a C-NOT gate, which is performed during error correction. Amazon’s researchers showed that the C-NOT operation did not disproportionately introduce bit-flip errors. This meant that after each round of error correction, the quantum computer still predominantly made phase-flip errors, so the simple, hardware-efficient error correction code could continue to be used.
AWS began working on designs for Ocelot as early as 2021, says Painter. Its development was a “full-stack problem.” To create high-performing qubits that could ultimately execute error correction, the researchers had to figure out a new way to grow tantalum, which is what their cat qubits are made of, on a silicon chip with as few atomic-scale defects as possible.
It’s a significant advance that AWS can now fabricate and control multiple cat qubits in a single device, says Puri. “Any work that goes toward scaling up new kinds of qubits, I think, is interesting,” she says. Still, there are years of development to go. Other experts have predicted that quantum computers will require thousands, if not millions, of qubits to perform a useful task. Amazon’s work “is a first step,” says Puri.
She adds that the researchers will need to further reduce the fraction of errors due to bit flips as they scale up the number of qubits.
Still, this announcement marks Amazon’s way forward. “This is an architecture we believe in,” says Painter. Previously, the company’s main strategy was to pursue conventional transmon qubits like Google’s and IBM’s, and they treated this cat qubit project as “skunkworks,” he says. Now, they’ve decided to prioritize cat qubits. “We really became convinced that this needed to be our mainline engineering effort, and we’ll still do some exploratory things, but this is the direction we’re going.” (The startup Alice & Bob, based in France, is also building a quantum computer made of cat qubits.)
As is, Ocelot basically is a demonstration of quantum memory, says Painter. The next step is to add more qubits to the chip, encode more information, and perform actual computations. But they have many challenges ahead, from how to attach all the wires to how to link multiple chips together. “Scaling is not trivial,” he says.
